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Wafer Level 3-D ICs Process Technology

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Cover of 'Wafer Level 3-D ICs Process Technology'

Table of Contents

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    Book Overview
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    Chapter 1 Overview of Wafer-Level 3D ICs
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    Chapter 2 Monolithic 3D Integrated Circuits
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    Chapter 3 Stacked CMOS Technologies
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    Chapter 4 Wafer-Bonding Technologies and Strategies for 3D ICs
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    Chapter 5 Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies
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    Chapter 6 Cu Wafer Bonding for 3D IC Applications
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    Chapter 7 Cu/Sn Solid–Liquid Interdiffusion Bonding
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    Chapter 8 An SOI-Based 3D Circuit Integration Technology
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    Chapter 9 3D Fabrication Options for High-Performance CMOS Technology
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    Chapter 10 3D Integration Based upon Dielectric Adhesive Bonding
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    Chapter 11 Direct Hybrid Bonding
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    Chapter 12 3D Memory
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    Chapter 13 Circuit Architectures for 3D Integration
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    Chapter 14 Thermal Challenges of 3D ICs
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    Chapter 15 Status and Outlook
Attention for Chapter 9: 3D Fabrication Options for High-Performance CMOS Technology
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