↓ Skip to main content
What is this page? Embed badge

Logic Synthesis and Verification Algorithms

Overview of attention for book
Cover of 'Logic Synthesis and Verification Algorithms'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Introduction
  3. Altmetric Badge
    Chapter 2 A Quick Tour of Logic Synthesis with the Help of a Simple Example
  4. Altmetric Badge
    Chapter 3 Boolean Algebras
  5. Altmetric Badge
    Chapter 4 Synthesis of Two-Level Circuits
  6. Altmetric Badge
    Chapter 5 Heuristic Minimization of Two-level Circuits
  7. Altmetric Badge
    Chapter 6 Binary Decision Diagrams (BDDs)
  8. Altmetric Badge
    Chapter 7 Models of Sequential Systems
  9. Altmetric Badge
    Chapter 8 Synthesis and Verification of Finite State Machines
  10. Altmetric Badge
    Chapter 9 Finite Automata
  11. Altmetric Badge
    Chapter 10 Multi-Level Logic Synthesis
  12. Altmetric Badge
    Chapter 11 Multi-Level Minimization
  13. Altmetric Badge
    Chapter 12 Automatic Test Generation for Combinational Circuits
  14. Altmetric Badge
    Chapter 13 Technology Mapping
Attention for Chapter 8: Synthesis and Verification of Finite State Machines
Altmetric Badge

Citations

dimensions_citation
2 Dimensions
Summary Dimensions citations
So far, Dimensions has found 2 publications that cite this research output.

2

The most recent citing publications are shown below. View all 2 publications that cite this research output on Dimensions.

This page shows the most recent citations of this research output.

Click here to find out how to access more activity.

This page is provided by Altmetric.