You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output.
Click here to find out more.
| Chapter title |
Synthesis and Verification of Finite State Machines
|
|---|---|
| Chapter number | 8 |
| Book title |
Logic Synthesis and Verification Algorithms
|
| Published by |
Springer, Boston, MA, January 2002
|
| DOI | 10.1007/0-306-47592-8_8 |
| Book ISBNs |
978-0-7923-9746-5, 978-0-306-47592-4
|