Logic Synthesis and Verification Algorithms
Springer US
Chapter title |
Binary Decision Diagrams (BDDs)
|
---|---|
Chapter number | 6 |
Book title |
Logic Synthesis and Verification Algorithms
|
Published by |
Springer, Boston, MA, January 2002
|
DOI | 10.1007/0-306-47592-8_6 |
Book ISBNs |
978-0-7923-9746-5, 978-0-306-47592-4
|
Country | Count | As % |
---|---|---|
India | 1 | 10% |
Unknown | 9 | 90% |
Readers by professional status | Count | As % |
---|---|---|
Student > Ph. D. Student | 1 | 10% |
Student > Postgraduate | 1 | 10% |
Unknown | 8 | 80% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 1 | 10% |
Engineering | 1 | 10% |
Unknown | 8 | 80% |