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Chapter title |
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits
|
---|---|
Chapter number | 24 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2011
|
DOI | 10.1007/978-3-642-24154-3_24 |
Book ISBNs |
978-3-64-224153-6, 978-3-64-224154-3
|
Authors |
Takumi Okuhira, Tohru Ishihara, Okuhira, Takumi, Ishihara, Tohru |