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Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Cover of 'Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 A Quick Method for Energy Optimized Gate Sizing of Digital Circuits
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    Chapter 2 Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures
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    Chapter 3 A System Level Approach to Multi-core Thermal Sensors Calibration
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    Chapter 4 Improving the Robustness of Self-timed SRAM to Variable Vdds
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    Chapter 5 Architecture Extensions for Efficient Management of Scratch-Pad Memory
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    Chapter 6 Pass Transistor Operation Modeling for Nanoscale Technologies
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    Chapter 7 Timing Modeling of Flipflops Considering Aging Effects
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    Chapter 8 Iterative Timing Analysis Considering Interdependency of Setup and Hold Times
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    Chapter 9 Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology
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    Chapter 10 Performance-Driven Clustering of Asynchronous Circuits
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    Chapter 11 Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing
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    Chapter 12 Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores
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    Chapter 13 Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks
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    Chapter 14 Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs
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    Chapter 15 Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique
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    Chapter 16 NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
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    Chapter 17 An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs
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    Chapter 18 Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution
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    Chapter 19 Using Silent Writes in Low-Power Traffic-Aware ECC
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    Chapter 20 SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging
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    Chapter 21 Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
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    Chapter 22 Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating
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    Chapter 23 A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts
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    Chapter 24 Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits
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    Chapter 25 C-elements for Hardened Self-timed Circuits
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    Chapter 26 High-Speed and Low-Power PID Structures for Embedded Applications
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    Chapter 27 Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits
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    Chapter 28 Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
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    Chapter 29 Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study
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    Chapter 30 A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
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    Chapter 31 Variability-Speed-Consumption Trade-off in Near Threshold Operation
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    Chapter 32 High Level Synthesis of Asynchronous Circuits from Data Flow Graphs
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    Chapter 33 A Secure D Flip-Flop against Side Channel Attacks
  35. Altmetric Badge
    Chapter 34 Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling
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Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Published by
Lecture notes in computer science, January 2011
DOI 10.1007/978-3-642-24154-3
ISBNs
978-3-64-224153-6, 978-3-64-224154-3
Authors

José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard

Editors

Ayala, José L., García-Cámara, Braulio, Prieto, Manuel, Ruggiero, Martino, Sicard, Gilles, Ayala, José L., García-Cámara, Braulio, Prieto, Manuel, Ruggiero, Martino, Sicard, Gilles

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 Attention Score in Context

Attention Score in Context

This research output has an Altmetric Attention Score of 1. This is our high-level measure of the quality and quantity of online attention that it has received. This Attention Score, as well as the ranking and number of research outputs shown below, was calculated when the research output was last mentioned on 25 December 2021.
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#20,233,547
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#6,982
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#170,086
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