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Post-Silicon Validation and Debug

Overview of attention for book
Cover of 'Post-Silicon Validation and Debug'

Table of Contents

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    Book Overview
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    Chapter 1 Post-Silicon SoC Validation Challenges
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    Chapter 2 SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness
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    Chapter 3 Structural Signal Selection for Post-Silicon Validation
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    Chapter 4 Simulation-Based Signal Selection
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    Chapter 5 Hybrid Signal Selection
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    Chapter 6 Post-Silicon Signal Selection Using Machine Learning
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    Chapter 7 Observability-Aware Post-Silicon Test Generation
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    Chapter 8 On-Chip Constrained-Random Stimuli Generation
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    Chapter 9 Test Generation and Lightweight Checking for Multi-core Memory Consistency
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    Chapter 10 Selection of Post-Silicon Hardware Assertions
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    Chapter 11 Debug Data Reduction Techniques
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    Chapter 12 High-Level Debugging of Post-Silicon Failures
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    Chapter 13 Post-Silicon Fault Localization with Satisfiability Solvers
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    Chapter 14 Coverage Evaluation and Analysis of Post-Silicon Tests with Virtual Prototypes
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    Chapter 15 Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis
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    Chapter 16 Network-on-Chip Validation and Debug
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    Chapter 17 Post-Silicon Validation of the IBM POWER8 Processor
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    Chapter 18 SoC Security Versus Post-Silicon Debug Conflict
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    Chapter 19 The Future of Post-Silicon Debug
Attention for Chapter 11: Debug Data Reduction Techniques
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