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Designing Reliable and Efficient Networks on Chips

Overview of attention for book
Cover of 'Designing Reliable and Efficient Networks on Chips'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 Designing Crossbar Based Systems
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    Chapter 3 Netchip Tool Flow for NoC Design
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    Chapter 4 Designing Standard Topologies
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    Chapter 5 Designing Custom Topologies
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    Chapter 6 Supporting Multiple Applications
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    Chapter 7 Supporting Dynamic Application Patterns
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    Chapter 8 Timing-Error Tolerant NoC Design
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    Chapter 9 Analysis of NoC Error Recovery Schemes
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    Chapter 10 Fault-Tolerant Route Generation
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    Chapter 11 NoC Support for Reliable On-Chip Memories
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    Chapter 12 Conclusions and Future Directions
Attention for Chapter 8: Timing-Error Tolerant NoC Design
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