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| Chapter title |
Timing-Error Tolerant NoC Design
|
|---|---|
| Chapter number | 8 |
| Book title |
Designing Reliable and Efficient Networks on Chips
|
| Published by |
Springer, Dordrecht, January 2009
|
| DOI | 10.1007/978-1-4020-9757-7_8 |
| Book ISBNs |
978-1-4020-9756-0, 978-1-4020-9757-7
|
| Authors |
Srinivasan Murali |