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Designing Reliable and Efficient Networks on Chips

Overview of attention for book
Attention for Chapter 3: Netchip Tool Flow for NoC Design
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Citations

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3 Mendeley
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Chapter title
Netchip Tool Flow for NoC Design
Chapter number 3
Book title
Designing Reliable and Efficient Networks on Chips
Published by
Springer, Dordrecht, January 2009
DOI 10.1007/978-1-4020-9757-7_3
Book ISBNs
978-1-4020-9756-0, 978-1-4020-9757-7
Authors

Srinivasan Murali

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 3 100%

Demographic breakdown

Readers by professional status Count As %
Unspecified 1 33%
Professor 1 33%
Student > Ph. D. Student 1 33%
Readers by discipline Count As %
Unspecified 1 33%
Computer Science 1 33%
Engineering 1 33%