Intelligent Memory Systems
Overview of attention for book
Table of Contents
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Altmetric BadgeBook Overview
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Altmetric BadgeChapter 1 A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
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Altmetric BadgeChapter 2 Software Controlled Reconfigurable On-chip Memory for High Performance Computing
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Altmetric BadgeChapter 3 Content-Based Prefetching: Initial Results
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Altmetric BadgeChapter 4 Memory System Support for Dynamic Cache Line Assembly
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Altmetric BadgeChapter 5 Adaptively Mapping Code in an Intelligent Memory Architecture
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Altmetric BadgeChapter 6 The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆
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Altmetric BadgeChapter 7 Memory Management in a PIM-Based Architecture
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Altmetric BadgeChapter 8 Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
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Altmetric BadgeChapter 9 FlexCache: A Framework for Flexible Compiler Generated Data Caching
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Altmetric BadgeChapter 10 Aggressive Memory-Aware Compilation
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Altmetric BadgeChapter 11 Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆
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Altmetric BadgeChapter 12 SAGE: A New Analysis and Optimization System for FlexRAM Architecture
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Altmetric BadgeChapter 13 Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
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Altmetric BadgeChapter 14 The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
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Altmetric BadgeChapter 15 Compiler-Directed Cache Line Size Adaptivity ⋆
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Altmetric BadgeChapter 16 Summary of Question/Answer Sessions for Workshop Presentations