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Intelligent Memory Systems

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Cover of 'Intelligent Memory Systems'

Table of Contents

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    Book Overview
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    Chapter 1 A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
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    Chapter 2 Software Controlled Reconfigurable On-chip Memory for High Performance Computing
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    Chapter 3 Content-Based Prefetching: Initial Results
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    Chapter 4 Memory System Support for Dynamic Cache Line Assembly
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    Chapter 5 Adaptively Mapping Code in an Intelligent Memory Architecture
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    Chapter 6 The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆
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    Chapter 7 Memory Management in a PIM-Based Architecture
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    Chapter 8 Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
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    Chapter 9 FlexCache: A Framework for Flexible Compiler Generated Data Caching
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    Chapter 10 Aggressive Memory-Aware Compilation
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    Chapter 11 Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆
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    Chapter 12 SAGE: A New Analysis and Optimization System for FlexRAM Architecture
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    Chapter 13 Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
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    Chapter 14 The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
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    Chapter 15 Compiler-Directed Cache Line Size Adaptivity ⋆
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    Chapter 16 Summary of Question/Answer Sessions for Workshop Presentations
Attention for Chapter 12: SAGE: A New Analysis and Optimization System for FlexRAM Architecture
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Summary
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Chapter title
SAGE: A New Analysis and Optimization System for FlexRAM Architecture
Chapter number 12
Book title
Intelligent Memory Systems
Published by
Springer, Berlin, Heidelberg, January 2001
DOI 10.1007/3-540-44570-6_12
Book ISBNs
978-3-54-042328-7, 978-3-54-044570-8
Authors

Tsung-Chuan Huang, Slo-Li Chu, Huang, Tsung-Chuan, Chu, Slo-Li

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