↓ Skip to main content
What is this page? Embed badge

Intelligent Memory Systems

Overview of attention for book
Cover of 'Intelligent Memory Systems'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
  3. Altmetric Badge
    Chapter 2 Software Controlled Reconfigurable On-chip Memory for High Performance Computing
  4. Altmetric Badge
    Chapter 3 Content-Based Prefetching: Initial Results
  5. Altmetric Badge
    Chapter 4 Memory System Support for Dynamic Cache Line Assembly
  6. Altmetric Badge
    Chapter 5 Adaptively Mapping Code in an Intelligent Memory Architecture
  7. Altmetric Badge
    Chapter 6 The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆
  8. Altmetric Badge
    Chapter 7 Memory Management in a PIM-Based Architecture
  9. Altmetric Badge
    Chapter 8 Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
  10. Altmetric Badge
    Chapter 9 FlexCache: A Framework for Flexible Compiler Generated Data Caching
  11. Altmetric Badge
    Chapter 10 Aggressive Memory-Aware Compilation
  12. Altmetric Badge
    Chapter 11 Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆
  13. Altmetric Badge
    Chapter 12 SAGE: A New Analysis and Optimization System for FlexRAM Architecture
  14. Altmetric Badge
    Chapter 13 Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
  15. Altmetric Badge
    Chapter 14 The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
  16. Altmetric Badge
    Chapter 15 Compiler-Directed Cache Line Size Adaptivity ⋆
  17. Altmetric Badge
    Chapter 16 Summary of Question/Answer Sessions for Workshop Presentations
Attention for Chapter 5: Adaptively Mapping Code in an Intelligent Memory Architecture
Altmetric Badge

Readers on

mendeley
2 Mendeley
Summary
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Adaptively Mapping Code in an Intelligent Memory Architecture
Chapter number 5
Book title
Intelligent Memory Systems
Published by
Springer, Berlin, Heidelberg, January 2001
DOI 10.1007/3-540-44570-6_5
Book ISBNs
978-3-54-042328-7, 978-3-54-044570-8
Authors

Yan Solihin, Jaejin Lee, Joseph Torrellas, Solihin, Yan, Lee, Jaejin, Torrellas, Joseph

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Unspecified 1 50%
Professor > Associate Professor 1 50%
Readers by discipline Count As %
Unspecified 1 50%
Computer Science 1 50%

This page is provided by Altmetric.