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Logic Synthesis and Verification Algorithms

Overview of attention for book
Logic Synthesis and Verification Algorithms
Springer US

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 A Quick Tour of Logic Synthesis with the Help of a Simple Example
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    Chapter 3 Boolean Algebras
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    Chapter 4 Synthesis of Two-Level Circuits
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    Chapter 5 Heuristic Minimization of Two-level Circuits
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    Chapter 6 Binary Decision Diagrams (BDDs)
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    Chapter 7 Models of Sequential Systems
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    Chapter 8 Synthesis and Verification of Finite State Machines
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    Chapter 9 Finite Automata
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    Chapter 10 Multi-Level Logic Synthesis
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    Chapter 11 Multi-Level Minimization
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    Chapter 12 Automatic Test Generation for Combinational Circuits
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    Chapter 13 Technology Mapping
Attention for Chapter 8: Synthesis and Verification of Finite State Machines
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Chapter title
Synthesis and Verification of Finite State Machines
Chapter number 8
Book title
Logic Synthesis and Verification Algorithms
Published by
Springer, Boston, MA, January 2002
DOI 10.1007/0-306-47592-8_8
Book ISBNs
978-0-7923-9746-5, 978-0-306-47592-4
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