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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

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Cover of 'Low Power Design with High-Level Power Estimation and Power-Aware Synthesis'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 Related Work
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    Chapter 3 Background
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    Chapter 4 Architectural Selection Using High Level Synthesis
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    Chapter 5 Statistical Regression Based Power Models
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    Chapter 6 Coprocessor Design Space Exploration Using High Level Synthesis
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    Chapter 7 Regression-Based Dynamic Power Estimation for FPGAs
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    Chapter 8 High Level Simulation Directed RTL Power Estimation
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    Chapter 9 Applying Verification Collaterals for Accurate Power Estimation
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    Chapter 10 Power Reduction Using High-Level Clock-Gating
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    Chapter 11 Model-Checking to Exploit Sequential Clock-Gating
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    Chapter 12 System Level Simulation Guided Approach for Clock-Gating
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    Chapter 13 Conclusions
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