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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Overview of attention for book
Attention for Chapter 10: Power Reduction Using High-Level Clock-Gating
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Chapter title
Power Reduction Using High-Level Clock-Gating
Chapter number 10
Book title
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Published by
Springer, New York, NY, January 2012
DOI 10.1007/978-1-4614-0872-7_10
Book ISBNs
978-1-4614-0871-0, 978-1-4614-0872-7
Authors

Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
United Arab Emirates 1 50%
Unknown 1 50%

Demographic breakdown

Readers by professional status Count As %
Professor > Associate Professor 1 50%
Other 1 50%
Readers by discipline Count As %
Computer Science 1 50%
Engineering 1 50%