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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

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Attention for Chapter 11: Model-Checking to Exploit Sequential Clock-Gating
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Chapter title
Model-Checking to Exploit Sequential Clock-Gating
Chapter number 11
Book title
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Published by
Springer, New York, NY, January 2012
DOI 10.1007/978-1-4614-0872-7_11
Book ISBNs
978-1-4614-0871-0, 978-1-4614-0872-7
Authors

Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla