ASIC/SoC Functional Design Verification

Overview of attention for book

Cover of 'ASIC/SoC Functional Design Verification'

Table of Contents

Attention for Chapter 17: Cache Memory Subsystem Verification: UVM Agent Based

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Citations

dimensions_citation: 32 Dimensions

Summary Dimensions citations

So far, Dimensions has found 32 publications that cite this research output.

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A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach

Book chapter (January 2024)

Heterogeneous SoC Design and Verification, HW/SW Co-Exploration, Co-Design, Co-Verification and Co-Debugging

Monograph (January 2024)

IngeniArs IP Cores for on-board high-speed data interfaces

Conference proceeding (October 2023)

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