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Mendeley readers
| Chapter title |
SystemVerilog Assertions (SVA)
|
|---|---|
| Chapter number | 6 |
| Book title |
ASIC/SoC Functional Design Verification
|
| Published by |
Springer, Cham, January 2018
|
| DOI | 10.1007/978-3-319-59418-7_6 |
| Book ISBNs |
978-3-31-959417-0, 978-3-31-959418-7
|
| Authors |
Ashok B. Mehta |
Mendeley readers
The data shown below were compiled from readership statistics for 6 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
| Country | Count | As % |
|---|---|---|
| Unknown | 6 | 100% |
Demographic breakdown
| Readers by professional status | Count | As % |
|---|---|---|
| Researcher | 2 | 33% |
| Student > Ph. D. Student | 1 | 17% |
| Student > Master | 1 | 17% |
| Unknown | 2 | 33% |
| Readers by discipline | Count | As % |
|---|---|---|
| Engineering | 3 | 50% |
| Computer Science | 1 | 17% |
| Unknown | 2 | 33% |