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ASIC/SoC Functional Design Verification

Overview of attention for book
Cover of 'ASIC/SoC Functional Design Verification'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 Functional Verification: Challenges and Solutions
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    Chapter 3 SystemVerilog Paradigm
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    Chapter 4 UVM (Universal Verification Methodology)
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    Chapter 5 Constrained Random Verification (CRV)
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    Chapter 6 SystemVerilog Assertions (SVA)
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    Chapter 7 SystemVerilog Functional Coverage (SFC)
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    Chapter 8 Clock Domain Crossing (CDC) Verification
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    Chapter 9 Low-Power Verification
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    Chapter 10 Static Verification (Formal-Based Technologies)
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    Chapter 11 ESL (Electronic System Level) Verification Methodology
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    Chapter 12 Hardware/Software Co-verification
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    Chapter 13 Analog/Mixed Signal (AMS) Verification
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    Chapter 14 SoC Interconnect Verification
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    Chapter 15 The Complete Product Design Life Cycle
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    Chapter 16 Voice Over IP (VoIP) Network SoC Verification
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    Chapter 17 Cache Memory Subsystem Verification: UVM Agent Based
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    Chapter 18 Cache Memory Subsystem Verification: ISS Based
Attention for Chapter 5: Constrained Random Verification (CRV)
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Citations

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Chapter title
Constrained Random Verification (CRV)
Chapter number 5
Book title
ASIC/SoC Functional Design Verification
Published by
Springer, Cham, January 2018
DOI 10.1007/978-3-319-59418-7_5
Book ISBNs
978-3-31-959417-0, 978-3-31-959418-7
Authors

Ashok B. Mehta

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 1 Mendeley reader of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 1 100%

Demographic breakdown

Readers by professional status Count As %
Professor > Associate Professor 1 100%
Readers by discipline Count As %
Computer Science 1 100%

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