Logic Synthesis and Optimization

Chapter 1 A New Exact Minimizer for Two-Level Logic Synthesis

Chapter 2 A New Graph Based Prime Computation Technique

Chapter 4 Network Optimization Using Don’t-Cares and Boolean Relations

Chapter 5 Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning

Chapter 6 A Partitioning Method for Area Optimization by Tree Analysis

Chapter 7 A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams

Chapter 8 Delay Models and Exact Timing Analysis

Chapter 9 Challenges to Dependable Asynchronous Processor Design

Chapter 10 Efficient Spectral Techniques for Logic Synthesis

Chapter 11 FPGA Design by Generalized Functional Decomposition

Chapter 12 Logic Synthesis with Exor Gates

Chapter 13 And-Exor Expressions and their Optimization

Chapter 14 A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams

Chapter 15 A New Technology Mapping Method Based on Concurrent Factorization and Mapping

Chapter 16 Gate Sizing for Cell-Based Designs