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Logic Synthesis and Optimization

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Cover of 'Logic Synthesis and Optimization'

Table of Contents

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    Book Overview
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    Chapter 1 A New Exact Minimizer for Two-Level Logic Synthesis
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    Chapter 2 A New Graph Based Prime Computation Technique
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    Chapter 3 Logic Synthesizers, The Transduction Method and Its Extension, Sylon
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    Chapter 4 Network Optimization Using Don’t-Cares and Boolean Relations
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    Chapter 5 Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning
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    Chapter 6 A Partitioning Method for Area Optimization by Tree Analysis
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    Chapter 7 A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams
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    Chapter 8 Delay Models and Exact Timing Analysis
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    Chapter 9 Challenges to Dependable Asynchronous Processor Design
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    Chapter 10 Efficient Spectral Techniques for Logic Synthesis
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    Chapter 11 FPGA Design by Generalized Functional Decomposition
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    Chapter 12 Logic Synthesis with Exor Gates
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    Chapter 13 And-Exor Expressions and their Optimization
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    Chapter 14 A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams
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    Chapter 15 A New Technology Mapping Method Based on Concurrent Factorization and Mapping
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    Chapter 16 Gate Sizing for Cell-Based Designs
Attention for Chapter 14: A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams
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Chapter title
A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams
Chapter number 14
Book title
Logic Synthesis and Optimization
Published by
Springer, Boston, MA, January 1993
DOI 10.1007/978-1-4615-3154-8_14
Book ISBNs
978-1-4613-6381-1, 978-1-4615-3154-8
Authors

Koichi Yasuoka, Yasuoka, Koichi

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