↓ Skip to main content
What is this page? Embed badge

Logic Synthesis and Optimization

Overview of attention for book
Cover of 'Logic Synthesis and Optimization'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 A New Exact Minimizer for Two-Level Logic Synthesis
  3. Altmetric Badge
    Chapter 2 A New Graph Based Prime Computation Technique
  4. Altmetric Badge
    Chapter 3 Logic Synthesizers, The Transduction Method and Its Extension, Sylon
  5. Altmetric Badge
    Chapter 4 Network Optimization Using Don’t-Cares and Boolean Relations
  6. Altmetric Badge
    Chapter 5 Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning
  7. Altmetric Badge
    Chapter 6 A Partitioning Method for Area Optimization by Tree Analysis
  8. Altmetric Badge
    Chapter 7 A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams
  9. Altmetric Badge
    Chapter 8 Delay Models and Exact Timing Analysis
  10. Altmetric Badge
    Chapter 9 Challenges to Dependable Asynchronous Processor Design
  11. Altmetric Badge
    Chapter 10 Efficient Spectral Techniques for Logic Synthesis
  12. Altmetric Badge
    Chapter 11 FPGA Design by Generalized Functional Decomposition
  13. Altmetric Badge
    Chapter 12 Logic Synthesis with Exor Gates
  14. Altmetric Badge
    Chapter 13 And-Exor Expressions and their Optimization
  15. Altmetric Badge
    Chapter 14 A Generation Method For Exor-Sum-of-Products Expressions Using Shared Binary Decision Diagrams
  16. Altmetric Badge
    Chapter 15 A New Technology Mapping Method Based on Concurrent Factorization and Mapping
  17. Altmetric Badge
    Chapter 16 Gate Sizing for Cell-Based Designs
Attention for Chapter 9: Challenges to Dependable Asynchronous Processor Design
Altmetric Badge

Citations

dimensions_citation
144 Dimensions

Readers on

mendeley
3 Mendeley
Summary Dimensions citations
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Challenges to Dependable Asynchronous Processor Design
Chapter number 9
Book title
Logic Synthesis and Optimization
Published by
Springer, Boston, MA, January 1993
DOI 10.1007/978-1-4615-3154-8_9
Book ISBNs
978-1-4613-6381-1, 978-1-4615-3154-8
Authors

Takashi Nanya, Nanya, Takashi

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 3 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
France 1 33%
Unknown 2 67%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 2 67%
Professor 1 33%
Readers by discipline Count As %
Computer Science 2 67%
Business, Management and Accounting 1 33%

This page is provided by Altmetric.