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Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

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Cover of 'Multi-Objective Optimization in Physical Synthesis of Integrated Circuits'

Table of Contents

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    Book Overview
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    Chapter 1 Timing Closure for Multi-Million-Gate Integrated Circuits
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    Chapter 2 State of the Art in Physical Synthesis
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    Chapter 3 Buffer Insertion During Timing-Driven Placement
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    Chapter 4 Bounded Transactional Timing Analysis
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    Chapter 5 Gate Sizing During Timing-Driven Placement
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    Chapter 6 Physically-Driven Logic Restructuring
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    Chapter 7 Logic Restructuring as an Aid to Physical Retiming
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    Chapter 8 Broadening the Scope of Optimization Using Partitioning
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    Chapter 9 Co-Optimization of Latches and Clock Networks
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    Chapter 10 Conclusions
Attention for Chapter 9: Co-Optimization of Latches and Clock Networks
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Chapter title
Co-Optimization of Latches and Clock Networks
Chapter number 9
Book title
Multi-Objective Optimization in Physical Synthesis of Integrated Circuits
Published by
Springer, New York, NY, January 2013
DOI 10.1007/978-1-4614-1356-1_9
Book ISBNs
978-1-4614-1355-4, 978-1-4614-1356-1
Authors

David A. Papa, Igor L. Markov, Papa, David A., Markov, Igor L.

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