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Logic Synthesis for Low Power VLSI Designs

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Cover of 'Logic Synthesis for Low Power VLSI Designs'

Table of Contents

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    Book Overview
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    Chapter 1 Introduction
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    Chapter 2 Technology Independent Power Analysis and Modeling
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    Chapter 3 Two-Level Logic Minimization in CMOS Circuits
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    Chapter 4 Two-Level Logic Minimization in PLAs
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    Chapter 5 Logic Restructuring for Low Power
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    Chapter 6 Logic Minimization for Low Power
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    Chapter 7 Technology Dependent Optimization for Low Power
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    Chapter 8 Post Mapping Structural Optimization for Low Power
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    Chapter 9 POSE: Power Optimization and Synthesis Environment
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    Chapter 10 Concluding Remarks
Attention for Chapter 8: Post Mapping Structural Optimization for Low Power
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