↓ Skip to main content
What is this page? Embed badge

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Overview of attention for book
Cover of 'Design for High Performance, Low Power, and Reliable 3D Integrated Circuits'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Regular Versus Irregular TSV Placement for 3D IC
  3. Altmetric Badge
    Chapter 2 Steiner Routing for 3D IC
  4. Altmetric Badge
    Chapter 3 Buffer Insertion for 3D IC
  5. Altmetric Badge
    Chapter 4 Low Power Clock Routing for 3D IC
  6. Altmetric Badge
    Chapter 5 Power Delivery Network Design for 3D IC
  7. Altmetric Badge
    Chapter 6 3D Clock Routing for Pre-bond Testability
  8. Altmetric Badge
    Chapter 7 TSV-to-TSV Coupling Analysis and Optimization
  9. Altmetric Badge
    Chapter 8 TSV Current Crowding and Power Integrity
  10. Altmetric Badge
    Chapter 9 Modeling of Atomic Concentration at the Wire-to-TSV Interface
  11. Altmetric Badge
    Chapter 10 Multi-objective Architectural Floorplanning for 3D IC
  12. Altmetric Badge
    Chapter 11 Thermal-Aware Gate-Level Placement for 3D IC
  13. Altmetric Badge
    Chapter 12 3D IC Cooling with Micro-Fluidic Channels
  14. Altmetric Badge
    Chapter 13 Mechanical Reliability Analysis and Optimization for 3D ICs
  15. Altmetric Badge
    Chapter 14 Impact of Mechanical Stress on Timing Variation for 3D IC
  16. Altmetric Badge
    Chapter 15 Chip/Package Co-analysis of Mechanical Stress for 3D IC
  17. Altmetric Badge
    Chapter 16 3D Chip/Package Co-analysis of Stress-Induced Timing Variations
  18. Altmetric Badge
    Chapter 17 TSV Interfacial Crack Analysis and Optimization
  19. Altmetric Badge
    Chapter 18 Ultra High Density Logic Designs Using Monolithic 3D Integration
  20. Altmetric Badge
    Chapter 19 Impact of TSV Scaling on 3D IC Design Quality
  21. Altmetric Badge
    Chapter 20 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
Attention for Chapter 18: Ultra High Density Logic Designs Using Monolithic 3D Integration
Altmetric Badge
Summary
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Ultra High Density Logic Designs Using Monolithic 3D Integration
Chapter number 18
Book title
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Published by
Springer, New York, NY, January 2013
DOI 10.1007/978-1-4419-9542-1_18
Book ISBNs
978-1-4419-9541-4, 978-1-4419-9542-1
Authors

Sung Kyu Lim

View on publisher site

This page is provided by Altmetric.