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The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Overview of attention for article published in Discover Nano, March 2018
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Title
The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
Published in
Discover Nano, March 2018
DOI 10.1186/s11671-018-2483-8
Pubmed ID
Authors

Wei Li, Hongxia Liu, Shulong Wang, Shupeng Chen, Qianqiong Wang

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 8 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 8 100%

Demographic breakdown

Readers by professional status Count As %
Student > Master 2 25%
Student > Bachelor 2 25%
Student > Ph. D. Student 1 13%
Unknown 3 38%
Readers by discipline Count As %
Engineering 2 25%
Nursing and Health Professions 1 13%
Materials Science 1 13%
Psychology 1 13%
Unknown 3 38%