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| Chapter title |
Modeling Finite State Machines with SystemVerilog
|
|---|---|
| Chapter number | 7 |
| Book title |
SystemVerilog For Design
|
| Published by |
Springer, Boston, MA, January 2004
|
| DOI | 10.1007/978-1-4757-6682-0_7 |
| Book ISBNs |
978-1-4757-6684-4, 978-1-4757-6682-0
|
| Authors |
Stuart Sutherland, Simon Davidmann, Peter Flake |