SystemVerilog For Design
Springer US
Chapter title |
SystemVerilog User-Defined and Enumerated Data Types
|
---|---|
Chapter number | 3 |
Book title |
SystemVerilog For Design
|
Published by |
Springer, Boston, MA, January 2004
|
DOI | 10.1007/978-1-4757-6682-0_3 |
Book ISBNs |
978-1-4757-6684-4, 978-1-4757-6682-0
|
Authors |
Stuart Sutherland, Simon Davidmann, Peter Flake |