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Applied Reconfigurable Computing

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Cover of 'Applied Reconfigurable Computing'

Table of Contents

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    Book Overview
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    Chapter 1 Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks
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    Chapter 2 A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
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    Chapter 3 Hierarchical Dynamic Power-Gating in FPGAs
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    Chapter 4 Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation
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    Chapter 5 ArchHDL: A Novel Hardware RTL Design Environment in C++
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    Chapter 6 Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA
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    Chapter 7 Preemptive Hardware Multitasking in ReconOS
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    Chapter 8 A Fully Parallel Particle Filter Architecture for FPGAs
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    Chapter 9 TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
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    Chapter 10 Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures
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    Chapter 11 SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs
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    Chapter 12 Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties
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    Chapter 13 Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components
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    Chapter 14 Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays
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    Chapter 15 Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip
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    Chapter 16 Survey on Real-Time Network-on-Chip Architectures
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    Chapter 17 Efficient SR-Latch PUF
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    Chapter 18 Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study
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    Chapter 19 Dual CLEFIA/AES Cipher Core on FPGA
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    Chapter 20 An Efficient and Flexible FPGA Implementation of a Face Detection System
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    Chapter 21 A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context
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    Chapter 22 A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank
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    Chapter 23 The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs
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    Chapter 24 A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures
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    Chapter 25 Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA
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    Chapter 26 A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
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    Chapter 27 Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures
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    Chapter 28 Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects
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    Chapter 29 Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments
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    Chapter 30 DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems
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    Chapter 31 Acceleration of Data Streaming Classification using Reconfigurable Technology
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    Chapter 32 On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach
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    Chapter 33 Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform
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    Chapter 34 A Challenge of Portable and High-Speed FPGA Accelerator
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    Chapter 35 Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array
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    Chapter 36 Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture
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    Chapter 37 Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization
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    Chapter 38 DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost
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    Chapter 39 A Flexible Multilayer Perceptron Co-processor for FPGAs
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    Chapter 40 Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs
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    Chapter 41 Towards Performance Modeling of 3D Memory Integrated FPGA Architectures
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    Chapter 42 Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL
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    Chapter 43 Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing
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    Chapter 44 SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
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    Chapter 45 Hardware Task Scheduling for Partially Reconfigurable FPGAs
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    Chapter 46 SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring
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    Chapter 47 DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications
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    Chapter 48 Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective
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    Chapter 49 Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach
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    Chapter 50 COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator
Attention for Chapter 4: Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation
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Chapter title
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation
Chapter number 4
Book title
Applied Reconfigurable Computing
Published in
Lecture notes in computer science, March 2015
DOI 10.1007/978-3-319-16214-0_4
Book ISBNs
978-3-31-916213-3, 978-3-31-916214-0

Ian Graves, Adam Procter, William L. Harrison, Michela Becchi, Gerard Allwein

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 6 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 6 100%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 3 50%
Student > Doctoral Student 1 17%
Professor 1 17%
Lecturer 1 17%
Readers by discipline Count As %
Computer Science 4 67%
Business, Management and Accounting 1 17%
Unknown 1 17%