↓ Skip to main content
What is this page? Embed badge

Logic Synthesis for Low Power VLSI Designs

Overview of attention for book
Logic Synthesis for Low Power VLSI Designs
Springer US

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Introduction
  3. Altmetric Badge
    Chapter 2 Technology Independent Power Analysis and Modeling
  4. Altmetric Badge
    Chapter 3 Two-Level Logic Minimization in CMOS Circuits
  5. Altmetric Badge
    Chapter 4 Two-Level Logic Minimization in PLAs
  6. Altmetric Badge
    Chapter 5 Logic Restructuring for Low Power
  7. Altmetric Badge
    Chapter 6 Logic Minimization for Low Power
  8. Altmetric Badge
    Chapter 7 Technology Dependent Optimization for Low Power
  9. Altmetric Badge
    Chapter 8 Post Mapping Structural Optimization for Low Power
  10. Altmetric Badge
    Chapter 9 POSE: Power Optimization and Synthesis Environment
  11. Altmetric Badge
    Chapter 10 Concluding Remarks
Attention for Chapter 10: Concluding Remarks
Altmetric Badge
Summary
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
Concluding Remarks
Chapter number 10
Book title
Logic Synthesis for Low Power VLSI Designs
Published by
Springer, Boston, MA, January 1998
DOI 10.1007/978-1-4615-5453-0_10
Book ISBNs
978-1-4613-7490-9, 978-1-4615-5453-0
Authors

Sasan Iman, Massoud Pedram, Iman, Sasan, Pedram, Massoud

View on publisher site
Timeline

Login to access the full chart related to this output.

If you don’t have an account, click here to discover Explorer

This page is provided by Altmetric.