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| Chapter title |
Modeling Finite State Machines with SystemVerilog
|
|---|---|
| Chapter number | 8 |
| Book title |
SystemVerilog for Design
|
| Published by |
Springer, Boston, MA, January 2006
|
| DOI | 10.1007/0-387-36495-1_8 |
| Book ISBNs |
978-0-387-33399-1, 978-0-387-36495-7
|