↓ Skip to main content

SystemVerilog for Design

Overview of attention for book
Attention for Chapter 3: SystemVerilog Literal Values and Built-in Data Types
Altmetric Badge

Citations

dimensions_citation
9 Dimensions
You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output. Click here to find out more.
Chapter title
SystemVerilog Literal Values and Built-in Data Types
Chapter number 3
Book title
SystemVerilog for Design
Published by
Springer, Boston, MA, January 2006
DOI 10.1007/0-387-36495-1_3
Book ISBNs
978-0-387-33399-1, 978-0-387-36495-7