VLSI: Integrated Systems on Silicon

Table of Contents

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   Book Overview
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   Chapter 1 A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing
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   Chapter 2 A VLSI architecture for real-time edge linking
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   Chapter 3 VLSI Implementation of Contour Extraction from Real Time Image Sequences
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   Chapter 4 An architecture for a 12 bits, low power integrated CMOS pressure sensor with thermal compensation
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   Chapter 5 On-line testing of analog circuits by adaptive filters
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   Chapter 6 A Multi-Mode Signature Analyzer for Analog and Mixed Circuits
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   Chapter 7 An All-Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB
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   Chapter 8 An ATM Switching Element with programmable capacity
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    Chapter 9 Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation
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    Chapter 10 A Low-Voltage Operational Transconductance Amplifier and Its Application to a Bandpass Gm-C Filter
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    Chapter 11 A Programmable Second Generation SI Integrator for Low-Voltage Applications
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    Chapter 12 Low-voltage current-mode analogue continuous-time filters
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    Chapter 13 A set of device generators for analogue and mixed-signal layout synthesis
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    Chapter 14 E-TSPC: Extended True Single-Phase-Clock CMOS circuit technique
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    Chapter 15 Noise and power programmability in semi-custom I/O buffers
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    Chapter 16 Charge Pump DPLL to Operate at High Frequencies
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    Chapter 17 A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates
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    Chapter 18 An Embedded Accelerator for Real World Computing
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    Chapter 19 Design of a Low Power 108-bit Conditional Sum Adder Using Energy Economized Pass-transistor Logic (EEPL)
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    Chapter 20 A novel globally asynchronous locally synchronous sliding window DFT implementation
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    Chapter 21 Unfolded Redundant CORDIC VLSI Architectures With Reduced Area and Power Consumption
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    Chapter 22 Multi-View Design of Asynchronous Micropipeline Systems using Rainbow
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    Chapter 23 High Level Synthesis of Protocols Described by a Formal Description Technique
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    Chapter 24 Matisse: a concurrent and object-oriented system specification language
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    Chapter 25 Library Free Technology Mapping
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    Chapter 26 An implicit formulation for exact BDD minimization of incompletely specified functions
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    Chapter 27 Sequential Logic Optimization with Implicit Retiming and Resynthesis
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    Chapter 28 Boolean Mapping based on Testing Techniques
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    Chapter 29 Testability Analysis of Circuits using Data-Dependent Power Management
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    Chapter 30 Data Sequencing for Minimum-transition Transmission
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    Chapter 31 Spurious Transitions in Adder Circuits : Analytical Modelling and Simulations
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    Chapter 32 Power Reduction Through Clock Gating by Symbolic Manipulation
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    Chapter 33 A Timing-Driven Floorplanning Algorithm with the Elmore Delay Model for Building Block Layout
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    Chapter 34 An Efficient Layout Style for Three-Metal CMOS Macro-Cells
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    Chapter 35 Coupled Circuit-Interconnect Modeling and Simulation
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    Chapter 36 Accurate static timing analysis for deep submicronic CMOS circuits
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    Chapter 37 A Time Driven Adder Generator Architecture
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    Chapter 38 User Guided High Level Synthesis
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    Chapter 39 Empirical Interconnect Crosstalk Characterization for High Level Synthesis
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    Chapter 40 Methods and tools for high and system level synthesis
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    Chapter 41 A New Frequency-domain Analog Test Generation Tool
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    Chapter 42 Boundary-Scan Testing for Mixed — Signal MCMs
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    Chapter 43 Stress Testing: A Low Cost Alternative for Burn-in
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    Chapter 44 Non-Monte Carlo Simulation and Sensitivity of Linear(ized) Analog Circuits under Parameter Variations
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    Chapter 45 Top-Down Design Methodology & Technology for Microsystems