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Chapter title |
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates
|
---|---|
Chapter number | 43 |
Book title |
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2002
|
DOI | 10.1007/3-540-45716-x_43 |
Book ISBNs |
978-3-54-044143-4, 978-3-54-045716-9
|
Authors |
M. Alioto, G. Palumbo, Alioto, M., Palumbo, G. |