Chapter 1 Design of High Performance Low Power Microprocessors

Chapter 3 Low Power Asynchronous Circuit Design: An FFT/IFFT Processor

Chapter 4 CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration

Chapter 5 A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture

Chapter 6 Memory Systems for Nano-computer

Chapter 7 Flash Memory

Chapter 8 CMOS-based Spin-Transfer Torque Magnetic Random Access Memory (ST–MRAM)

Chapter 9 Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities

Chapter 10 High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies

Chapter 11 Timing Circuit Design in High Performance DRAM

Chapter 12 Overview and Scaling Prospect of Ferroelectric Memories