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CMOS Processors and Memories

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Cover of 'CMOS Processors and Memories'

Table of Contents

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    Book Overview
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    Chapter 1 Design of High Performance Low Power Microprocessors
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    Chapter 2 Towards High-Performance and Energy-Efficient Multi-core Processors
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    Chapter 3 Low Power Asynchronous Circuit Design: An FFT/IFFT Processor
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    Chapter 4 CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration
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    Chapter 5 A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture
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    Chapter 6 Memory Systems for Nano-computer
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    Chapter 7 Flash Memory
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    Chapter 8 CMOS-based Spin-Transfer Torque Magnetic Random Access Memory (ST–MRAM)
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    Chapter 9 Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities
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    Chapter 10 High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies
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    Chapter 11 Timing Circuit Design in High Performance DRAM
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    Chapter 12 Overview and Scaling Prospect of Ferroelectric Memories
Attention for Chapter 4: CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration
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Chapter title
CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration
Chapter number 4
Book title
CMOS Processors and Memories
Published by
Springer, Dordrecht, January 2010
DOI 10.1007/978-90-481-9216-8_4
Book ISBNs
978-9-04-819215-1, 978-9-04-819216-8
Authors

Dan Hammerstrom, Mazad S. Zaveri, Hammerstrom, Dan, Zaveri, Mazad S.

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