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Interconnect-Centric Design for Advanced SoC and NoC

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Cover of 'Interconnect-Centric Design for Advanced SoC and NoC'

Table of Contents

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    Book Overview
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    Chapter 1 System-on-Chip-Challenges in the Deep-Sub-Micron Era
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    Chapter 2 Wires as Interconnects
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    Chapter 3 Global Interconnect Analysis
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    Chapter 4 Design Methodologies for on-Chip Inductive Interconnect
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    Chapter 5 Clock Distribution for High Performance Designs
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    Chapter 6 Error-Tolerant Interconnect Schemes
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    Chapter 7 Power Reduction Coding for Buses
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    Chapter 8 Bus Structures in Network-on-Chips
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    Chapter 9 From Buses to Networks
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    Chapter 10 Arbitration and Routing Schemes for on-Chip Packet Networks
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    Chapter 11 Self-Timed Approach for Noise Reduction in NoC Reduction in NoC
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    Chapter 12 Formal Communication Modeling and Refinement
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    Chapter 13 Network-Centric System-Level Model for Multiprocessor Soc Simulation
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    Chapter 14 Socket-Based Design Using Decoupled Interconnects
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    Chapter 15 Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV
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    Chapter 16 A Brunch from the Coffee Table-Case Study in NoC Platform Design
Attention for Chapter 11: Self-Timed Approach for Noise Reduction in NoC Reduction in NoC
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