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Computer Aided Verification

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Cover of 'Computer Aided Verification'

Table of Contents

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    Book Overview
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    Chapter 1 Taming infinite state spaces
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    Chapter 2 Silence is golden: Branching bisimilarity is decidable for context-free processes
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    Chapter 3 Computing distinguishing formulas for branching bisimulation
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    Chapter 4 Compositional checking of satisfaction
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    Chapter 5 An action based framework for verifying logical and behavioural properties of concurrent systems
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    Chapter 6 A linear-time model-checking algorithm for the alternation-free modal mu-calculus
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    Chapter 7 Automatic temporal verification of buffer systems
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    Chapter 8 Mechanically checked proofs of kernel specifications
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    Chapter 9 A top down approach to the formal specification of SCI cache coherence
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    Chapter 10 Integer programming in the analysis of concurrent systems
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    Chapter 11 The lotos model of a fault protected system and its verification using a petri net based approach
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    Chapter 12 Error diagnosis in finite communicating systems
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    Chapter 13 Temporal precondition verification of design transformations
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    Chapter 14 PAM: A process algebra manipulator
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    Chapter 15 The Concurrency Workbench with priorities
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    Chapter 16 A proof assistant for PSF
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    Chapter 17 Avoiding state explosion by composition of minimal covering graphs
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    Chapter 18 “On the fly” verification of behavioural equivalences and preorders
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    Chapter 19 Bounded-memory algorithms for verification on-the-fly
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    Chapter 20 Generating BDDs for symbolic model checking in CCS
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    Chapter 21 Vectorized symbolic model checking of computation tree logic for sequential machine verification
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    Chapter 22 Functional extension of symbolic model checking
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    Chapter 23 An automated proof technique for finite-state machine equivalence
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    Chapter 24 From data structure to process structure
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    Chapter 25 Checking for language inclusion using simulation preorders
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    Chapter 26 A semantic driven method to check the fineteness of CCS processes
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    Chapter 27 Using the HOL prove assistant for proving the correctness of term rewriting rules reducing terms of sequential behavior
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    Chapter 28 Mechanizing a proof by induction of process algebra specifications in higher order logic
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    Chapter 29 A two-level formal verification methodology using HOL and COSMOS
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    Chapter 30 Efficient algorithms for verification of equivalences for probabilistic processes
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    Chapter 31 Partial-order model checking: A guide for the perplexed
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    Chapter 32 Using partial orders for the efficient verification of deadlock freedom and safety properties
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    Chapter 33 Complexity results for POMSET languages
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    Chapter 34 Mechanically verifying safety and liveness properties of delay insensitive circuits
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    Chapter 35 Automating most parts of hardware proofs in HOL
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    Chapter 36 An overview and synthesis on timed process algebras
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    Chapter 37 Minimum and maximum delay problems in realtime systems
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    Chapter 38 Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic
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    Chapter 39 Verifying properties of HMS machine specifications of real-time systems
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    Chapter 40 A linear time process algebra
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    Chapter 41 Deciding properties of regular real timed processes
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    Chapter 42 An algebra of Boolean processes
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    Chapter 43 Comparing generic state machines
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    Chapter 44 An automata theoretic approach to Temporal Logic
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Title
Computer Aided Verification
Published by
Springer Berlin Heidelberg, January 2006
DOI 10.1007/3-540-55179-4
ISBNs
978-3-54-055179-9, 978-3-54-046763-2
Editors

Larsen, Kim G., Skou, Arne

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