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Timeline
Chapter title |
Optimizing Synchronous Circuitry by Retiming (Preliminary Version)
|
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Chapter number | 7 |
Book title |
Third Caltech Conference on Very Large Scale Integration
|
Published by |
Springer, Berlin, Heidelberg, January 1983
|
DOI | 10.1007/978-3-642-95432-0_7 |
Book ISBNs |
978-3-54-012369-9, 978-3-64-295432-0
|
Authors |
Charles E. Leiserson, Flavio M. Rose, James B. Saxe, Leiserson, Charles E., Rose, Flavio M., Saxe, James B. |