Third Caltech Conference on Very Large Scale Integration

Table of Contents

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   Book Overview
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   Chapter 1 Practical Experience With VLSI Methodology
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   Chapter 2 CAPRI: A Design Methodology and a Silicon Compiler for VLSI Circuits Specified by Algorithms
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   Chapter 3 Design of a High Performance VLSI Processor
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   Chapter 4 Fundamental Issues in the Electrical Design of VLSI Circuits
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   Chapter 5 Crystal: A Timing Analyzer for nMOS VLSI Circuits
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   Chapter 6 TV: An nMOS Timing Analyzer
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   Chapter 7 Optimizing Synchronous Circuitry by Retiming (Preliminary Version)
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   Chapter 8 A New Channel Routing Algorithm
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    Chapter 9 River Routing: Methodology and Analysis
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    Chapter 10 Area and Delay Penalties in Restructurable Wafer-Scale Arrays
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    Chapter 11 Verification of VLSI Designs
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    Chapter 12 A Hierarchical Simulator Based on Formal Semantics
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    Chapter 13 Trace Theory and the Definition of Hierarchical Components
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    Chapter 14 Deriving Circuits from Programs
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    Chapter 15 Self-Timed IC Design with PPL’s
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    Chapter 16 A Self-Timed Static RAM
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    Chapter 17 Design of the PSC: A Programmable Systolic Chip
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    Chapter 18 The VLSI Design of a Reed-Solomon Encoder Using Berlekamp’s Bit-Serial Multiplier Algorithm
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    Chapter 19 A VLSI Chess Legal Move Generator
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    Chapter 20 New VLSI Architectures with Reduced Hardware
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    Chapter 21 Dumbo, A Schematic-to-Layout Compiler
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    Chapter 22 Macrocell Design for Concurrent Signal Processing
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    Chapter 23 A Case Study of the F.I.R.S.T. Silicon Compiler