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Cryptographic Hardware and Embedded Systems – CHES 2005

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Cover of 'Cryptographic Hardware and Embedded Systems – CHES 2005'

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Resistance of Randomized Projective Coordinates Against Power Analysis
  3. Altmetric Badge
    Chapter 2 Templates as Master Keys
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    Chapter 3 A Stochastic Model for Differential Side Channel Cryptanalysis
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    Chapter 4 A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis
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    Chapter 5 Further Hidden Markov Model Cryptanalysis
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    Chapter 6 Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
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    Chapter 7 Short Memory Scalar Multiplication on Koblitz Curves
  9. Altmetric Badge
    Chapter 8 Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 μP
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    Chapter 9 SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers
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    Chapter 10 Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
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    Chapter 11 Design of Testable Random Bit Generators
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    Chapter 12 Successfully Attacking Masked AES Hardware Implementations
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    Chapter 13 Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
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    Chapter 14 Masking at Gate Level in the Presence of Glitches
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    Chapter 15 Bipartite Modular Multiplication
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    Chapter 16 Fast Truncated Multiplication for Cryptographic Applications
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    Chapter 17 Using an RSA Accelerator for Modular Inversion
  19. Altmetric Badge
    Chapter 18 Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
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    Chapter 19 EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA
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    Chapter 20 Cryptographic Hardware and Embedded Systems – CHES 2005
  22. Altmetric Badge
    Chapter 21 Security Evaluation Against Electromagnetic Analysis at Design Time
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    Chapter 22 On Second-Order Differential Power Analysis
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    Chapter 23 Improved Higher-Order Side-Channel Attacks with FPGA Experiments
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    Chapter 24 Secure Data Management in Trusted Computing
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    Chapter 25 Data Remanence in Flash Memory Devices
  27. Altmetric Badge
    Chapter 26 Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment
  28. Altmetric Badge
    Chapter 27 DPA Leakage Models for CMOS Logic Circuits
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    Chapter 28 The “Backend Duplication” Method
  30. Altmetric Badge
    Chapter 29 Hardware Acceleration of the Tate Pairing in Characteristic Three
  31. Altmetric Badge
    Chapter 30 Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
  32. Altmetric Badge
    Chapter 31 AES on FPGA from the Fastest to the Smallest
  33. Altmetric Badge
    Chapter 32 A Very Compact S-Box for AES
Attention for Chapter 26: Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment
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Citations

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Chapter title
Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment
Chapter number 26
Book title
Cryptographic Hardware and Embedded Systems – CHES 2005
Published by
Springer, Berlin, Heidelberg, August 2005
DOI 10.1007/11545262_26
Book ISBNs
978-3-54-028474-1, 978-3-54-031940-5
Authors

Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede, Tiri, Kris, Hwang, David, Hodjat, Alireza, Lai, Bo-Cheng, Yang, Shenglin, Schaumont, Patrick, Verbauwhede, Ingrid

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 61 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
France 1 2%
Unknown 60 98%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 17 28%
Student > Master 11 18%
Researcher 7 11%
Student > Doctoral Student 4 7%
Student > Postgraduate 3 5%
Other 9 15%
Unknown 10 16%
Readers by discipline Count As %
Computer Science 30 49%
Engineering 12 20%
Physics and Astronomy 3 5%
Mathematics 2 3%
Arts and Humanities 1 2%
Other 2 3%
Unknown 11 18%