Cryptographic Hardware and Embedded Systems – CHES 2005

Table of Contents

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   Book Overview
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   Chapter 1 Resistance of Randomized Projective Coordinates Against Power Analysis
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   Chapter 2 Templates as Master Keys
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   Chapter 3 A Stochastic Model for Differential Side Channel Cryptanalysis
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   Chapter 4 A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis
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   Chapter 5 Further Hidden Markov Model Cryptanalysis
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   Chapter 6 Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
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   Chapter 7 Short Memory Scalar Multiplication on Koblitz Curves
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   Chapter 8 Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 μP
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    Chapter 9 SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers
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    Chapter 10 Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
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    Chapter 11 Design of Testable Random Bit Generators
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    Chapter 12 Successfully Attacking Masked AES Hardware Implementations
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    Chapter 13 Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
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    Chapter 14 Masking at Gate Level in the Presence of Glitches
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    Chapter 15 Bipartite Modular Multiplication
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    Chapter 16 Fast Truncated Multiplication for Cryptographic Applications
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    Chapter 17 Using an RSA Accelerator for Modular Inversion
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    Chapter 18 Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
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    Chapter 19 EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA
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    Chapter 20 Cryptographic Hardware and Embedded Systems – CHES 2005
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    Chapter 21 Security Evaluation Against Electromagnetic Analysis at Design Time
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    Chapter 22 On Second-Order Differential Power Analysis
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    Chapter 23 Improved Higher-Order Side-Channel Attacks with FPGA Experiments
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    Chapter 24 Secure Data Management in Trusted Computing
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    Chapter 25 Data Remanence in Flash Memory Devices
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    Chapter 26 Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment
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    Chapter 27 DPA Leakage Models for CMOS Logic Circuits
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    Chapter 28 The “Backend Duplication” Method
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    Chapter 29 Hardware Acceleration of the Tate Pairing in Characteristic Three
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    Chapter 30 Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
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    Chapter 31 AES on FPGA from the Fastest to the Smallest
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    Chapter 32 A Very Compact S-Box for AES