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| Chapter title |
Completeness of the Reduced Form
|
|---|---|
| Chapter number | 6 |
| Book title |
Formal Semantics and Proof Techniques for Optimizing VHDL Models
|
| Published by |
Springer, Boston, MA, January 1999
|
| DOI | 10.1007/978-1-4615-5123-2_6 |
| Book ISBNs |
978-1-4613-7331-5, 978-1-4615-5123-2
|
| Authors |
Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey |