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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Overview of attention for book
Attention for Chapter 7: Interval Temporal Logic
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Citations

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21 Mendeley
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Chapter title
Interval Temporal Logic
Chapter number 7
Book title
Formal Semantics and Proof Techniques for Optimizing VHDL Models
Published by
Springer, Boston, MA, January 1999
DOI 10.1007/978-1-4615-5123-2_7
Book ISBNs
978-1-4613-7331-5, 978-1-4615-5123-2
Authors

Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 21 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Portugal 1 5%
Norway 1 5%
Brazil 1 5%
United Kingdom 1 5%
Japan 1 5%
Unknown 16 76%

Demographic breakdown

Readers by professional status Count As %
Student > Ph. D. Student 6 29%
Researcher 5 24%
Professor 4 19%
Student > Doctoral Student 1 5%
Student > Master 1 5%
Other 3 14%
Unknown 1 5%
Readers by discipline Count As %
Computer Science 15 71%
Engineering 3 14%
Mathematics 1 5%
Unknown 2 10%