Gate-Controlled WSe2 Transistors Using a Buried Triple-Gate Structure

Overview of attention for article published in Discover Nano, November 2016

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So far, Altmetric has seen 4 patents that reference this research output.

Integrated circuit with vertical structures on nodes of a grid

Grant US-11171142-B2

United States of America

Microelectronic device with a memory element utilizing stacked vertical devices

Grant US-11164879-B2

United States of America

Buried conductive layer supplying digital circuits

Grant US-10833089-B2

United States of America

Microelectronic device utilizing stacked vertical devices

Grant US-10804266-B2

United States of America

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