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Computer Aided Verification

Overview of attention for book
Computer Aided Verification
Springer International Publishing

Table of Contents

  1. Altmetric Badge
    Book Overview
  2. Altmetric Badge
    Chapter 1 Satisfiability Checking for Mission-Time LTL
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    Chapter 2 High-Level Abstractions for Simplifying Extended String Constraints in SMT
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    Chapter 3 Alternating Automata Modulo First Order Theories
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    Chapter 4 Q3B: An Efficient BDD-based SMT Solver for Quantified Bit-Vectors
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    Chapter 5 cvc4sy: Smart and Fast Term Enumeration for Syntax-Guided Synthesis
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    Chapter 6 Incremental Determinization for Quantifier Elimination and Functional Synthesis
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    Chapter 7 Loop Summarization with Rational Vector Addition Systems
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    Chapter 8 Invertibility Conditions for Floating-Point Formulas
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    Chapter 9 Numerically-Robust Inductive Proof Rules for Continuous Dynamical Systems
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    Chapter 10 Icing: Supporting Fast-Math Style Optimizations in a Verified Compiler
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    Chapter 11 Sound Approximation of Programs with Elementary Functions
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    Chapter 12 Formal Verification of Quantum Algorithms Using Quantum Hoare Logic
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    Chapter 13 SecCSL: Security Concurrent Separation Logic
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    Chapter 14 Reachability Analysis for AWS-Based Networks
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    Chapter 15 Verification of Threshold-Based Distributed Algorithms by Decomposition to Decidable Logics
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    Chapter 16 Gradual Consistency Checking
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    Chapter 17 Checking Robustness Against Snapshot Isolation
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    Chapter 18 Efficient Verification of Network Fault Tolerance via Counterexample-Guided Refinement
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    Chapter 19 On the Complexity of Checking Consistency for Replicated Data Types
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    Chapter 20 Communication-Closed Asynchronous Protocols
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    Chapter 21 Interpolating Strong Induction
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    Chapter 22 Verifying Asynchronous Event-Driven Programs Using Partial Abstract Transformers
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    Chapter 23 Inferring Inductive Invariants from Phase Structures
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    Chapter 24 Termination of Triangular Integer Loops is Decidable
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    Chapter 25 AliveInLean: A Verified LLVM Peephole Optimization Verifier
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    Chapter 26 Automated Parameterized Verification of CRDTs
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    Chapter 27 What’s Wrong with On-the-Fly Partial Order Reduction
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    Chapter 28 Integrating Formal Schedulability Analysis into a Verified OS Kernel
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    Chapter 29 Rely-Guarantee Reasoning About Concurrent Memory Management in Zephyr RTOS
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    Chapter 30 Violat: Generating Tests of Observational Refinement for Concurrent Objects
Attention for Chapter 4: Q3B: An Efficient BDD-based SMT Solver for Quantified Bit-Vectors
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Chapter title
Q3B: An Efficient BDD-based SMT Solver for Quantified Bit-Vectors
Chapter number 4
Book title
Computer Aided Verification
Published by
Springer, Cham, July 2019
DOI 10.1007/978-3-030-25543-5_4
Book ISBNs
978-3-03-025542-8, 978-3-03-025543-5
Authors

Martin Jonáš, Jan Strejček, Jonáš, Martin, Strejček, Jan

View on publisher site
Mendeley readers

Mendeley readers

The data shown below were compiled from readership statistics for 2 Mendeley readers of this research output. Click here to see the associated Mendeley record.

Geographical breakdown

Country Count As %
Unknown 2 100%

Demographic breakdown

Readers by professional status Count As %
Professor > Associate Professor 1 50%
Unknown 1 50%
Readers by discipline Count As %
Unknown 2 100%

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