Chapter 1 A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Chapter 2 An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication

Chapter 4 Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS

Chapter 5 Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields

Chapter 6 Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis

Chapter 7 ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

Chapter 8 Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems

Chapter 9 Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis

Chapter 10 Improved Test Solutions for COTS-Based Systems in Space Applications

Chapter 11 Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection

Chapter 12 Assessment of Low-Budget Targeted Cyberattacks Against Power Systems

Chapter 13 Efficient Hardware/Software Co-design for NTRU