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Mendeley readers
Chapter title |
Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization
|
---|---|
Chapter number | 17 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2003
|
DOI | 10.1007/978-3-540-39762-5_17 |
Book ISBNs |
978-3-54-020074-1, 978-3-54-039762-5
|
Authors |
Sonia López, Óscar Garnica, Ignacio Hidalgo, Juan Lanchares, Román Hermida, López, Sonia, Garnica, Óscar, Hidalgo, Ignacio, Lanchares, Juan, Hermida, Román |
Mendeley readers
The data shown below were compiled from readership statistics for 5 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
France | 1 | 20% |
Unknown | 4 | 80% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor | 2 | 40% |
Student > Ph. D. Student | 2 | 40% |
Professor > Associate Professor | 1 | 20% |
Readers by discipline | Count | As % |
---|---|---|
Computer Science | 4 | 80% |
Engineering | 1 | 20% |