You are seeing a free-to-access but limited selection of the activity Altmetric has collected about this research output.
Click here to find out more.
Mendeley readers
Chapter title |
State Encoding for Low-Power FSMs in FPGA
|
---|---|
Chapter number | 5 |
Book title |
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
|
Published by |
Springer, Berlin, Heidelberg, September 2003
|
DOI | 10.1007/978-3-540-39762-5_5 |
Book ISBNs |
978-3-54-020074-1, 978-3-54-039762-5
|
Authors |
Luis Mengibar, Luis Entrena, Michael G Lorenz, Raúl Sánchez-Reillo, Mengibar, Luis, Entrena, Luis, Lorenz, Michael G, Sánchez-Reillo, Raúl |
Mendeley readers
The data shown below were compiled from readership statistics for 9 Mendeley readers of this research output. Click here to see the associated Mendeley record.
Geographical breakdown
Country | Count | As % |
---|---|---|
Malaysia | 1 | 11% |
Unknown | 8 | 89% |
Demographic breakdown
Readers by professional status | Count | As % |
---|---|---|
Professor > Associate Professor | 2 | 22% |
Student > Ph. D. Student | 1 | 11% |
Researcher | 1 | 11% |
Other | 1 | 11% |
Unknown | 4 | 44% |
Readers by discipline | Count | As % |
---|---|---|
Engineering | 4 | 44% |
Computer Science | 1 | 11% |
Unknown | 4 | 44% |